Digital signal processing apparatus, such as interface circuits for data storage disk drives, frequently require the capability of executing signal processing operations with highly accurate timing, irrespective of the frequency and time of occurrence of a basic system clock that controls the majority of events within a system. Attempting to generate a timing signal asynchronously with respect to the system clock by using multiple occurrences of the clock signal is not necessarily precise, or even possible, particularly where the initiation point of the timing signal is selected at a time that falls immediately subsequent to a transition in the system clock. For example, in a data processing system operating off a precision 20 MHz. crystal reference, clock signals occur at intervals of 50 ns. By simply counting five consecutive clock signals one could ostensibly generate a 250 ns. delay pulse. However, if the clock count begins at a time which is slightly subsequent to the most recent clock signals (e.g. one ns. later), then the actual time of occurrence of a transition edge of the intended 250 ns. pulse may be retarded by nearly one clock cycle (49 ns. in the example). Because of this inherent uncertainty window in using a fixed system clock, it is common practice to achieve a desired delay using `trimmable` components, such as RC delay circuits, and monostable multivibrators (one-shots), and precision delay lines. Unfortunately, within a given circuit architecture, the insertion of individual delay components cannot always be readily accomplished and often requires the use of a separate `off-chip` timing circuit, which increases hardware complexity and is subject to drift. Precision delay lines are not subject to the drift problem; however, they add considerable cost and, consequently, are most practically employed in `higher ticket` items such as memories.